Many integrated circuits have signal lanes that support transmission and/or receipt of data signals. Those signal lanes can include circuitry (e.g., serializer/deserializer, or SERDES, circuits) to prepare bit data for transmission and/or to recover bit data after receipt. A standard figure of merit (FoM) for such circuitry is margin. For example, a larger margin measurement can indicate that the circuit is more tolerant of jitter and/or other non-idealities that can impact reliable recovery of data received over a channel. Sinusoidal jitter tolerance (SJT) testing is an industry standard measure of inherent margin inside the SERDES as it relates to clock data recovery (CDR). Typically, sinusoidal jitter tolerance involves injection of sinusoidal jitter into the data path using laboratory test equipment to determine the tolerance of the SERDES to that injected jitter (e.g., by monitoring the ability of the SERDES to track the injected jitter, etc.). While use of such test equipment tends to be effective, they tend to have various limitations. For example, such test equipment is often very expensive, unavailable in operational contexts (e.g., outside the context of a test lab), and tend only to measure margins relating to the particular test environment (e.g., they cannot accurately account for additional non-idealities of the system environment in which the circuits will be deployed).